rggen 0.27.1
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Gemfile:
=
复制到剪贴板
已复制!
安装:
=
Runtime 依赖 (6):
rggen-c-header
~> 0.2.0
rggen-core
~> 0.27.0
rggen-default-register-map
~> 0.27.0
rggen-markdown
~> 0.23.0
rggen-spreadsheet-loader
~> 0.22.1
rggen-systemverilog
~> 0.27.0
Development 依赖 (1):
bundler
>= 0