origen_verilog 0.2.1

A parser and generator for Verilog (IEEE 1364)

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Versões:

0.6.3 - September 24, 2019 (117 KB)
0.6.2 - June 12, 2019 (117 KB)
0.6.1 - June 06, 2019 (117 KB)
0.6.0 - May 16, 2019 (117 KB)
0.5.2 - December 20, 2018 (117 KB)
0.2.1 - December 13, 2017 (115 KB)

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Runtime Dependencies (2):

ast ~> 2

treetop >= 0

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Donos:

Autores:

Stephen McGinty

SHA 256 checksum:

6fb9a816925194bfa3b3e820f46d3ed682f1f259253692d3cdb2da95313c7e54