rggen 0.11.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map specifications.

Gemfile:
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Versões:

0.33.2 - June 11, 2024 (16 KB)
0.33.1 - January 23, 2024 (16 KB)
0.33.0 - January 22, 2024 (16 KB)
0.32.2 - January 03, 2024 (16 KB)
0.32.0 - December 28, 2023 (16 KB)
0.11.0 - August 11, 2019 (46,5 KB)

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Runtime Dependencies (3):

rggen-core ~> 0.11

rggen-spreadsheet-loader ~> 0.10

rggen-systemverilog ~> 0.11

Development Dependencies (1):

bundler >= 0

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Donos:

Pushed by:

Autores:

Taichi Ishitani

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Total de downloads 93.437

Desta versão 1.772

Licença:
MIT

Versão Requerida do Ruby: >= 2.3

New versions require MFA: true

Links:

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